Labels:text | screenshot | map | rectangle | plan OCR: FIGURE 2 Architecture ot Core processor. Dual-ported SPRAN nstruchon cache Two independent duas-ported blocks JTAG Processor port Test & .Ador mulation Binck 1 DAGS DAG2 sequence !! PM Address bus External port: Acdr bus Dit Address but MUX: PM Data Des 48/64 connect 32/40/64 Date bus: Barrel shifter Serial ports ALU Link ports Boats buffers